In semiconductor circuit devices, finer pattern techniques are being developed and integration densities are increasing every year. One of the dominant limiting factors with the decreasing size and increasing densities is package pin count. Accordingly, circuit designers are generally searching for ways to increase the density inside a package and at the same time conserve precious I/O pins. One area that circuit designers have been trying to conserve I/O pins is in the area of debug I/O.
One currently used method to conserve debug I/O pins is phase muxing onto existing busses, which involves debug circuits sharing I/O drivers and pins with other "normal" or functional circuits. This tends to make debugging very slow and complex, due to the loading and the fact that the circuitry sharing the I/O drivers is sometimes the very circuitry that needs to be debugged. It also consumes expensive die space and can interfere with the I/O used in normal operation if the circuits to be debugged are the ones which share the I/O. Moreover, this method still requires a considerable number of dedicated debug I/O pins, for example, signals which can not be phase muxed. The lower performance of this method also requires more bits for debug, and thus, more pads and pins are needed for debug.
Another commonly used debug method is referred to as piggy backing or low visibility phase muxing, which involves using shared I/O drivers during normal operation only when they are idle. The disadvantages of piggy backing are complexity, cost and lower observability.
Another commonly used method for debugging is to use dedicated pins, which obviously is very expensive when pins are at a premium. Moreover, debug I/O is present on every chip and gets shipped with every chip sold, although they are only used during the rigorous testing or characterization in the lab. Pin count dominates package cost and is the cost driver index vendors use when pricing their packages. Accordingly, this is an extremely expensive debug solution.
Accordingly, there is a need in the field of semiconductor design for a method of debug testing that is higher in performance, that has fewer parasitic losses, and that requires fewer die pads and fewer package I/O pins. There is also a need for the ability to observe internal chip operation at very high speed and very high performance levels, while at the same time saving die space, package I/O pins and cost.